The present invention relates to a read only storage device installed in semiconductor devices, particularly to a mask ROM (read only memory) into which information is written at the manufacturing stage.
Recently, in a mask ROM, as the manufacturing process gets finer and the storage capacity increases, it has become an important issue to improve the production yield. In order to improve the production yield, the technique for replacing a defective memory cell with a spare memory cell is proposed. A specific description will be provided below with reference to the drawings.
FIG. 13 is a circuit diagram showing a configuration of a prior art semiconductor device. The semiconductor device in FIG. 13 comprises a control circuit 3, an address input circuit 4, a row decoder 5, a memory cell array 6, a column decoder 7, a sense amplifier circuit 8, an output circuit 9, an address storage circuit 10, a data storage circuit 11, and a switching circuit 20 which inputs the data from the memory cell array 6 and the data from the data storage circuit 11, selects either of these two pieces of data based on the output information from the address storage circuit 10 and outputs the selected data.
FIG. 2 shows a configuration example of the address storage circuit 10. The address storage circuit 10 stores the address of a memory cell to be replaced (a defective memory cell) in the memory cell array 6. In FIG. 2, the address storage circuit 10 inputs address signals AD1–ADn. The address signals AD1–ADn connect to the gate terminals of transistors TRP1–TRPn and the inputs of inverters 201–20n. The outputs of the inverters 201–20n connect to the gate terminals of transistors TRN1–TRNn. The source of each of the transistors TRP1–TRPn and TRN1–TRNn is grounded and the drain thereof is connected via the corresponding one of fuse elements FAP1–n and FAN1–n to the input of two serially connected inverters 221–222. An output signal (control signal) RAD from these two serially connected inverters 221–222 is transmitted to the data storage circuit 11 and the switching circuit 20.
When there is a defective memory cell, in the manufacturing step, the fuse elements of the address storage circuit 10 in FIG. 2 are disconnected by laser in response to the values of the address signals AD1–ADn of the defective memory cell. Namely, if the address signal ADi of the defective memory cell (i: an arbitrary integer of 1 through n) is 1 (high level), the fuse element FAPi is disconnected, whereas, if the address signal ADi of the defective memory cell is 0 (low level), the fuse element FANi is disconnected. Afterwards, when the address signals AD1–ADn coincide with the address of the defective memory cell, the control signal RAD is driven high, whereas, when the address signals AD1–ADn constitute the address of other than the defective memory cell, the control signal RAD is driven low.
FIG. 3 shows a configuration example of the data storage circuit 11. The data storage circuit 11 stores m-bit data of the memory cell to be replaced (defective memory cell) in the memory cell array 6. The data storage circuit 11 inputs the control signal RAD from the address storage circuit 10, which is further input to the gate terminals of transistors TRD1–TRDm. The source of each transistor is grounded, and the drain thereof is connected via the corresponding one of fuse elements FD1–m to the input of each of two-stage inverters 301–30m. Output data RD1–m from the two-stage inverters 301–30m is transmitted to the switching circuit 20.
When there is a defective memory cell, the m-bit data which should have been stored in the memory cell is stored in m circuit(s) of the data storage circuit 11. Specifically, in the manufacturing step, the address signals AD1–ADn of the defective memory cell are input to the address storage circuit 10 and the control signal RAD is driven high. The data storage circuit 11 inputs the high control signal RAD. The transistors TRD1–TRDm of the data storage circuit 11 are all brought into conduction.
When data DATAj (j: an arbitrary integer of 1 through m) is high in response to m-bit data DATA1–DATAm which should have been stored in the defective memory cell, the fuse element FDj of the bit is disconnected by laser. If the DATAj is 0 (low level), the fuse element FDj is not disconnected. As a result, when the control signal RAD is driven high (if the address signals AD1–ADn of the defective memory cell are input to the semiconductor device), the data storage circuit 11 outputs the m-bit data of the defective memory cell.
FIG. 14 shows a configuration example of the switching circuit 20 of the prior art semiconductor device. M selection circuits 1401–140m of the switching circuit 20 input output data SO1–SOm coming via the sense amplifier from the memory cell array 6 and the output data RD1–RDm coming from the data storage circuit 11 (each of these two pieces of the output data comprises m bits), select either the output data SO1–SOm or RD1–RDm according to the control signal RAD output from the address storage circuit 10 and output the selected data as data DI1–m. When the control signal RAD is high, the switching circuit 20 outputs the data RD1–m, whereas, when the control signal RAD is low, the switching circuit 20 outputs the data SO1–m.
As described above, when there is a defective memory cell in the memory cell array 6, the address of the defective memory cell is stored by disconnecting the corresponding fuses among the fuses FAP1–n and FAN1–n of the address storage circuit 10. The data of the defective memory cell is stored by disconnecting the corresponding fuses among the fuses FD1–m of the data storage circuit 11. When the address input signals AD1–n coincide with the address of the defective memory cell, the control signal RAD output from the address storage circuit 10 is driven high, whereby the switching circuit 20 outputs the data coming from the data storage circuit 11, and from the output circuit 9, the data coming from the data storage circuit 11 is output. When the address signals AD1–n don't coincide with the address of the defective memory cell, the control signal RAD output from the address storage circuit 10 is driven low, whereby the switching circuit 20 outputs the data coming from the memory cell array 6. The output circuit 9 outputs the data coming from the memory cell array 6 according to a selection signal CS1 (storage device selection information) (if the mask ROM core is selected by the selection signal CS1).
In recent years, semiconductor devices, with increasing sophistication, have come with a plurality of mask ROM cores (referred to as a storage device) which are of high-speed reading type and of low capacity. The prior art semiconductor device had the switching circuit 20 between the sense amplifier circuit 8 of the mask ROM core and the output circuit 9. The transmission delay time from when the address storage circuit 10 inputs the address signals AD1–n until the data read from the data storage circuit 11 arrives at the switching circuit 20 is longer than the transmission delay time from when the address circuit 4 inputs the address signals AD1–n until the data read from the memory cell array 6 of high-speed reading type arrives at the switching circuit 20. Therefore, the prior art semiconductor device has a problem that the data read time in the case of replacing the defective memory cell with the address storage circuit 10 and the data storage circuit 11 gets longer than the usual data read time.
In general, fuse elements constitute a very large chip area. Since the prior art semiconductor device has a configuration where the address storage circuit and the data storage circuit for replacing the data of the defective memory cell are provided per ROM core (a configuration where the switching from the data of the defective memory cell to the replacement data is performed in each mask ROM core), there is a problem that the chip area of the semiconductor device having a plurality of mask ROM cores increases.
The present invention intends to solve the above-mentioned problem and is intended to provide a semiconductor device wherein the data read time in the case of replacing the defective memory cell with the address storage circuit and the data storage circuit is equal to the data read time in the case of reading data from the memory cell array.
The present invention further intends to provide a semiconductor device which has a configuration where a plurality of mask ROM cores share the address storage circuit and the data storage circuit so that two or more mask ROM cores are provided while the chip area is small.